1. Field of the Invention
The present invention relates to a memory cell circuitry device, and more particularly to a method of programming a non-volatile memory cell. The programming current is controlled through use of current pulldown circuitry at the source gate of the cell. The pulldown circuitry is rate controllable, and can also be configured to vary the rate in order to compensate for device process variations.
2. Description of Related Art
Non-volatile memory cells include devices such as CMOS, NMOS, and bipolar transistor devices which are configured to perform as EPROMs (Electrically Programmable Read Only Memories) and EEPROMs (Electrically Erasable Programmable Read Only Memories). The storage transistor used in a memory cell is typically a variation of an NMOS transistor wherein the cell stores charge on a section of polysilicon which is floating in an area of silicon dioxide above the P-substrate material of the device. This floating area, referred to as a floating gate, is located between the P-substrate material, which includes a drain and source gate, and a control gate. The silicon dioxide is typically about 8 to 12 nanometers thick and insulates the floating gate polysilicon from the control gate above the N-channel device.
An electrically induced avalanche injection mechanism is used to charge the floating gate with electrons from the substrate. A current is induced to flow through the substrate by application of a high voltage across the drain and source gates of the device. As this current flows, various hot electrons will jump from the substrate material to the floating gate thereby creating a useful charge on the device. This charge is then retained until it is discharged by various techniques including, for instance, application of ultraviolet light or X-rays, or formation and use of electrical tunneling effects (e.g. Fowler-Nordheim tunneling mechanism).
In applying a voltage across the substrate, if the voltage is too high, the related adverse effects such a punchthrough and drain-turn-on will impact the reliability and predictability of programming the memory device. In actual product configurations, there are typically other cells arranged in parallel with the programming cell. Such arrangements may further cause the adverse effects to get more severe and make the programming current larger than desired, which is inefficient. Such concerns are even more prevalent as the size of the memory cell devices shrink and the substrate thicknesses decrease. A thinner substrate and related layers are more susceptible to damage from excessive programming currents.
Still another concern with present devices is the ability to have sufficient current available to program the device. A trend today is create devices which use less power, and thereby may only contain a single power supply for a multi-cell array or configuration. An internal high voltage is created via a charge pumping circuit, and is thereafter coupled to the drain gate of the memory device to achieve the necessary voltage drop across the drain and source gates. Without a sufficient voltage, the memory device cannot be adequately programmed.
For any given voltage across the cell, the current flow through the device will be affected by the relatively conductivity of the cell. Such conductivity will be affected by process variations in forming the cell. While manufacturers strive for known results and conformity in the formation of devices, process variations are inevitable to some degree, and expensive to control. If, for instance, the overall process variations in forming the device produce a higher conductivity, then a higher programming current will be created across the device upon the application of a given voltage. An unpredictably high current can produce punch through and like problems mentioned above. On the other hand, if process variations produce a lower conductivity, then a lower programming current will be created upon application of the same given voltage. Unpredictably lower currents can lead to ineffective programming of the cell.
Prior attempts have been made at biasing a memory cell circuit to compensate for device processing characteristics. In U.S. Pat. No. 5,218,571, a circuit is provided which uses a process dependant voltage reference generator during the programming cycle. When the transistor conductivity is low, a lower source voltage is set. This serves to increase the drain-to-source voltage drop, and thereby increases the resulting programming current through the cell. Conversely, when the transistor conductivity is high, a higher source voltage is set which serves to decrease the drain-to-source differential, and thereby decreases the resulting current. This solution, however, does not serve to control the rate of the programming current. The reference voltage is set to a certain level, dependant upon process variations, and held at that level in order to program the memory cell device.
Accordingly, what is needed in this field is a method and apparatus which allows for a controlled rate of programming a memory cell. As programming conditions are applied to a memory cell, the programming current should be controllable at a slow enough rate as to prevent hot electron effects such as punch through. The programming current should also be variable, as needed in order to achieve the current rate programming goal, and also be responsive to device process variations.